Electroluminescent displays are advantageous by virtue of their low operating voltage with respect to cathode ray tubes, their superior image quality, wide viewing angle and fast response time over liquid crystal displays, and their superior gray scale capability and thinner profile than plasma display panels.
As shown in FIGS. 1 and 2, an electroluminescent display has two intersecting sets of parallel electrically conductive address lines called rows (ROW 1, ROW 2, etc.) and columns (COL 1, COL 2, etc.) that are disposed on either side of a phosphor film encapsulated between two dielectric films. A pixel is defined as the intersection point between a row and a column. Thus, FIG. 2 is a cross-sectional view through the pixel at the intersection of ROW 4 and COL 4, in FIG. 1. Each pixel is illuminated by the application of a voltage across the intersection of row and column defining the pixel.
Matrix addressing entails applying a voltage below the threshold voltage to a row while simultaneously applying a modulation voltage of the opposite polarity to each column that bisects that row. The voltages on the row and the column are summed to give a total voltage in accordance with the illumination desired on the respective sub-pixels, thereby generating one line of the image. An alternate scheme is to apply the maximum sub-pixel voltage to the row and apply a modulation voltage of the same polarity to the columns. The magnitude of the modulation voltage is up to the difference between the maximum voltage and the threshold voltage to set the pixel voltages in accordance with the desired image. In either case, once each row is addressed, another row is addressed in a similar manner until all of the rows have been addressed. Rows that are not addressed are left at open circuit.
The sequential addressing of all rows constitutes a complete frame. Typically, a new frame is addressed at least about 50 times per second to generate what appears to the human eye as a flicker-free video image.
In order to generate realistic video images with flat panel displays, it is important to provide the required luminosity ratios between gray levels where the driving voltage is regulated to facilitate gray scale control. This is particularly true for electroluminescent displays where gray scale control is exercised through control of the output voltage on the column drivers for the display.
Traditional thin film electroluminescent displays employing thin dielectric layers that sandwich a phosphor film interposed between driving electrodes are not amenable to gray scale control through modulation of the column voltage, due to the very abrupt and non-linear nature of the luminance turn-on as the driving voltage is increased. By way of contrast, electroluminescent displays employing thick, high dielectric constant dielectric layered pixels have a nearly linear dependence on the luminance above the threshold voltage, and are thus more amenable to gray scale control by voltage modulation. However, even in this case if the gray scale voltage levels are generated by equally spaced voltage levels then the luminance values of the gray levels are not in the correct ratios for video applications.
The gray level information in a video signal is digitally encoded as an 8 bit number. These digitally coded gray levels are used to generate reference voltage levels Vg that facilitate the generation of luminance levels (Lg) for each gray level in accordance with an empirical relationship of the form:Lg=f(Vg)=Anγ  (Equation 1)
where f(Vg) represents that the luminance is a function of the voltage applied to a pixel and A is a constant, n is the gray level number and γ is typically between 2 and 0.2.5.
An electroluminescent (EL) display driver with gray scale capability resembles a digital-to analog (D/A) device with an output buffer. The purpose is to convert incoming gray scale 8-bit digital data from the video source to an analog output voltage for panel driving. There are various types of gray scale drivers, each employing a different method of performing the necessary digital-to-analog conversion. The present invention is related to the type of gray scale drivers that use a linear ramping voltage as a means of performing the D/A conversion. For this type of driver, the digital gray level code is first converted to a pulse-width through a counter operated by a fixed frequency clock. The time duration of this pulse-width is a representation of, and corresponds to, the gray level digital code. The pulse-width output of the counter controls a capacitor sample-and-hold circuit which operates in conjunction with an externally generated linear voltage ramp to achieve the pulse-width to voltage conversion. Since the linear ramp has a linear relationship between the output voltage and time, the pulse-width representation of the digital code therefore generates a linear gray level voltage at the driver output. The luminance created for each level is then dependent on the relationship between the voltage applied to a pixel and the pixel luminance, which is the basic electro-optical characteristic of the particular panel. This luminance-voltage characteristic is normally different from the ideal characteristic, and therefore Gamma correction is necessary.
The relationship between the voltage applied to a pixel and its luminance is typified by the curve in FIG. 3. The luminance begins to rise above the threshold voltage in a nonlinear fashion for the first few volts above the threshold, and then rises in an approximate linear fashion before saturating at a fixed luminance. The portion of the curve used for display operation is the initially rising portion and the linear portion. The effects of differential loading of the driver outputs complicate the relationship. To negate the effect of variable loading and to improve the energy efficiency of the display, a driver employing a sinusoidal drive voltage with a resonant energy recovery feature is typically employed. Such a driver is disclosed in U.S. patent application Ser. No. 09/504,472 (now U.S. Pat. No. 6,448,950) and U.S. patent application Ser. No. 10/036,002 (now U.S. Pat. No. 6,819,308), the contents of which are incorporated herein by reference. However, it is nonetheless desirable to tailor the output voltage for the gray levels to generate a gray scale response similar to that described by the empirical relationship given by Equation 1.
According to the prior art, circuits are known for gray scale compensation in flat panel displays.
For example, U.S. Pat. No. 5,652,600 (Khormaei et al) discloses a gray-scale correction system for EL displays which involves illuminating first selected pixel electrodes with data signals during a first subframe time period of the received image and thereafter energizing a second set of selected pixel electrodes with data signals during the next subframe time period where the first and second illumination signals have predetermined characteristics that differ from each other. The structure of the EL display is complex, and does not suggest the use of a reference voltage generator that employs a non-linear voltage ramp to generate gray-scale levels having correct luminance levels in an EL display.
U.S. Pat. No. 5,812,104 (Kapoor et al) discloses the use of different levels of pixel luminance to achieve correct gray-scaling in an EL display. The '104 patent acknowledges the problem of prior art ramp generators to adequately vary the rate of the ramped voltage signal from a constant value throughout the ramp. In response to that, the '104 patent sets forth a gray-scale stepped ramp voltage generator constructed so that various step sizes may be obtained during each of the voltage steps. The disclosed circuit is very complex and is not capable of generating an intensity dynamic range of 256×256 (gamma=2.0 per equation 1) between lowest and highest gray levels. Further, the use of TFEL devices is not amenable to achieving the gray levels to meet television standards, as set forth above.
U.S. Pat. No. 6,417,825 (Stewart et al) discloses an EL display with gray-scale and a ramp voltage that may be made non-linear. However, the '825 patent is applicable only to active matrix EL and to frame rate modulation, not passive matrix EL and voltage modulation.
The following prior art is of background interest to the present invention:
U.S. Pat. No. 5,227,863 (Bilbrey et al) U.S. Pat. No. 5,550,557 (Kapoor et al)